risc-v may be at risk of creating a self-perpetuating case of circular reporting
the article in the post links to this arstechnica article, which in turn links to this eetimes article, which is i believe reporting false information, and this is by no means the first time the first time i saw this link of articles being referenced when talking about risc-v
i have absolutely no experience designing chips obviously, so maybe someone competent can come in and elaborate/correct this, but the eetimes article completely ignores that there are two clusters of cores in the M1 when comparing it’s performance, also claiming M1 coremarks score way lower than it actually is, so even if you ignore different performance/watt for cores in these clusters, and just take the power consumption on average per core, you end up with M1 actual per watt performance being ~200 times higher than reported in the article
regardless of that this risc-v core still ends up with better performance/watt, but such errors in the article are kind of worrying, and don’t do favors when regarding the legitimacy of it’s claims
additionally it has no info on how this performance/watt would scale, which is a huge factor
anyway, i wish anyone designing non-x86/arm processors all the best, because fuck that, but i have a fear that even though the ISA is freely available for anyone, most will probably end up facing the fact that designing and even more importantly manufacturing chips is an enormous challenge, which in an of itself is very prohibitive, and as a result we’ll end up with not two but maybe five companies designing risc-v cpus, all produced on a single factory using exclusive contracts that prohibit competitors, and all the cpus will be some bs internet of shit stuff chips, or chips with extremely specific applications, that would be useless to the general public, definitely should have licensed risc-v under GPL 😉
all of this may be completely wrong, i don’t actually know what i’m doing…
There are a lot of advantages to using risc-v over x86. Using a risc instruction set is key to how M1 works. There’s a great explanation here, but basically what it comes down to is that having fixed size instructions allows easily and predictably chopping up incoming instructions into blocks and then checking if they have any inter-dependencies. Any instructions that don’t can be executed in parallel. This is something that’s not possible to do with a cisc architecture.
If Chinese companies abandon x86/arm architectures then they will also be able to abandon all the baggage associated with them the way Apple did with M1. Starting fresh opens up possibilities for efficient SoC architectures that don’t need a bus and have shared memory between different processing components.
With China seeing this as a national security concern there will be state level resources devoted towards designing these chips, and I expect to see interesting things come out of that in the near future.
The biggest question is whether Chinese companies will choose to keep their tech open source or simply base it off risc-v and close it up.
i never criticized risc ISAs or risc-v in particular, and never said they don’t have any advantages compared to cisc ISAs, the former by all means have huge potential, i haven’t even compared the two…
my comment is simply criticizing wildly false claims made by a company in an article that is very often liked when discussing risc-v
Yeah, that’s fair the claims about performance are sensational. The part of the article I linked that I thought was interesting was that there does appear to be a serious push to start using risc-v architecture in China.
I agree that designing and manufacturing chips is an enormous challenge, but it’s not an insurmountable problem either. If China starts devoting resources towards this at state level we’ll almost certainly see chips that can rival what Apple achieved with M1 in the near future. This is a matter of national security for China, and that translates into effectively unlimited resources being devoted to solving the problem of having a domestic chip design.
risc-v may be at risk of creating a self-perpetuating case of circular reporting
the article in the post links to this arstechnica article, which in turn links to this eetimes article, which is i believe reporting false information, and this is by no means the first time the first time i saw this link of articles being referenced when talking about risc-v
i have absolutely no experience designing chips obviously, so maybe someone competent can come in and elaborate/correct this, but the eetimes article completely ignores that there are two clusters of cores in the M1 when comparing it’s performance, also claiming M1 coremarks score way lower than it actually is, so even if you ignore different performance/watt for cores in these clusters, and just take the power consumption on average per core, you end up with M1 actual per watt performance being ~200 times higher than reported in the article
regardless of that this risc-v core still ends up with better performance/watt, but such errors in the article are kind of worrying, and don’t do favors when regarding the legitimacy of it’s claims
additionally it has no info on how this performance/watt would scale, which is a huge factor
anyway, i wish anyone designing non-x86/arm processors all the best, because fuck that, but i have a fear that even though the ISA is freely available for anyone, most will probably end up facing the fact that designing and even more importantly manufacturing chips is an enormous challenge, which in an of itself is very prohibitive, and as a result we’ll end up with not two but maybe five companies designing risc-v cpus, all produced on a single factory using exclusive contracts that prohibit competitors, and all the cpus will be some bs internet of shit stuff chips, or chips with extremely specific applications, that would be useless to the general public, definitely should have licensed risc-v under GPL 😉
all of this may be completely wrong, i don’t actually know what i’m doing…
There are a lot of advantages to using risc-v over x86. Using a risc instruction set is key to how M1 works. There’s a great explanation here, but basically what it comes down to is that having fixed size instructions allows easily and predictably chopping up incoming instructions into blocks and then checking if they have any inter-dependencies. Any instructions that don’t can be executed in parallel. This is something that’s not possible to do with a cisc architecture.
If Chinese companies abandon x86/arm architectures then they will also be able to abandon all the baggage associated with them the way Apple did with M1. Starting fresh opens up possibilities for efficient SoC architectures that don’t need a bus and have shared memory between different processing components.
With China seeing this as a national security concern there will be state level resources devoted towards designing these chips, and I expect to see interesting things come out of that in the near future.
The biggest question is whether Chinese companies will choose to keep their tech open source or simply base it off risc-v and close it up.
i never criticized risc ISAs or risc-v in particular, and never said they don’t have any advantages compared to cisc ISAs, the former by all means have huge potential, i haven’t even compared the two…
my comment is simply criticizing wildly false claims made by a company in an article that is very often liked when discussing risc-v
Yeah, that’s fair the claims about performance are sensational. The part of the article I linked that I thought was interesting was that there does appear to be a serious push to start using risc-v architecture in China.
I agree that designing and manufacturing chips is an enormous challenge, but it’s not an insurmountable problem either. If China starts devoting resources towards this at state level we’ll almost certainly see chips that can rival what Apple achieved with M1 in the near future. This is a matter of national security for China, and that translates into effectively unlimited resources being devoted to solving the problem of having a domestic chip design.