I imagine Intel and AMD must be freaking out right about now. This is a great article explaining why x86 fundamentally can’t compete with RISC and SOC architecture.
TLDR is that SOC allows efficient sharing of memory without the need for the bus with both CPU and GPU can read and write to the same memory locations. Meanwhile, RISC instructions are fixed length which allows the chip to read a batch of instructions find ones that can be computed independently and run them in parallel. This facilitates massive parallelization that’s inherently impossible to do using CISC approach.
I imagine Intel and AMD must be freaking out right about now. This is a great article explaining why x86 fundamentally can’t compete with RISC and SOC architecture.
TLDR is that SOC allows efficient sharing of memory without the need for the bus with both CPU and GPU can read and write to the same memory locations. Meanwhile, RISC instructions are fixed length which allows the chip to read a batch of instructions find ones that can be computed independently and run them in parallel. This facilitates massive parallelization that’s inherently impossible to do using CISC approach.