The article doesn’t really go into it but what’s a typical yield for chips like that? That’s great they’re on a smaller dye but if you’re trashing half of them it seems you’re not quite there yet.
It seems pretty poor, especially for 2023. This article from four years ago has TSMC touting an 80% yield rate on their new-at-the-time 5nm process. Still, the fact that Huawei is able to produce 7nm parts at all is something of a victory. Huawei is probably around five years behind TSMC at this point but may be able to close that gap over time.
That’s based on TSMC’s own test chip not an actual customer’s. 17.92 mm² is incredibly tiny when SoCs, CPUs and GPUs range in size from 100 to 600 mm² increasing the proportion of chips with defects as the number of chips on the wafer drops.
From that very article
In that case, let us take the 100 mm2 die as an example of the first mobile processors coming out of TSMC’s process. Again, taking the die as square, a defect rate of 1.271 per cm2 would afford a yield of 32.0%.
As TSMC themselves designed the chip, they definitely followed all their design rules for that process to maximize yield. No customer would do that.
But have no fear. What normally happens is your foundry company will come to you with a list of design rules and hints. If you follow all of the guidelines, the foundry will guarantee that they can produce your chip and that it will work. In other words, do what we tell you to do, and your chip will yield.
The problem is that if you follow every last one of these design rules and hints your chip won’t be any faster than it was on the older manufacturing process. Your yield will be about the same but your cost will be higher since you’ll bloat your design taking into account these “hints”.
Generally between process nodes the size of the wafer doesn’t change. We were at 200mm wafers for a while and now modern fabs use 300mm wafers. The transistor size does shrink however, so in theory you could fit more die on a wafer with each process shrink.
The problem is with any new process, the cost per wafer goes up. It’s a new process, most likely more complex, and thus the wafer cost is higher. If the wafer costs are 50% higher, then you need to fit at least 50% more die on each wafer in order to break even with your costs on the old process. In reality you actually need to fit more than 50% die per wafer on the new process because yields usually suck at the start. But if you follow the foundry’s guidelines to guarantee yield, you won’t even be close to breaking even.
The end result is you get zero benefit from moving to the new process. That’s not an option for anyone looking to actually use Moore’s Law to their advantage. Definitely not for a GPU company.
The solution is to have some very smart people in your company that can take these design rules and hints the foundry provides, and figure out which ones can be ignored, and ways to work around the others. This is an area where ATI and NVIDIA differ greatly.
If you’re trashing half of them, that’s just means fabrication is more expensive. This seems to be an acceptable cost for Huawei, and I imagine SMIC will get subsidies to offset the cost in the short term. The important part is that SMIC can now produce commercially viable 7nm chips domestically, and they’re only going to get better at doing it going forward.
The article doesn’t really go into it but what’s a typical yield for chips like that? That’s great they’re on a smaller dye but if you’re trashing half of them it seems you’re not quite there yet.
It seems pretty poor, especially for 2023. This article from four years ago has TSMC touting an 80% yield rate on their new-at-the-time 5nm process. Still, the fact that Huawei is able to produce 7nm parts at all is something of a victory. Huawei is probably around five years behind TSMC at this point but may be able to close that gap over time.
That’s based on TSMC’s own test chip not an actual customer’s. 17.92 mm² is incredibly tiny when SoCs, CPUs and GPUs range in size from 100 to 600 mm² increasing the proportion of chips with defects as the number of chips on the wafer drops.
From that very article
As TSMC themselves designed the chip, they definitely followed all their design rules for that process to maximize yield. No customer would do that.
Anand explains this in one of his articles.
If you’re trashing half of them, that’s just means fabrication is more expensive. This seems to be an acceptable cost for Huawei, and I imagine SMIC will get subsidies to offset the cost in the short term. The important part is that SMIC can now produce commercially viable 7nm chips domestically, and they’re only going to get better at doing it going forward.