Especially with how normal memory tiering is nowadays, especially in the datacenter (Intel’s bread and butter) now that you can stick a box of memory on a CXL network and put the memory from your last gen servers you just retired into said box for a third or fourth tier of memory before swapping. And the fun not tiered memory stuff the CXL enables. Really CXL just enables so much cool stuff that it’s going to be incredible once that starts hitting small single row datacenters
I wonder why both isn’t possible, build some into the chip but leave some DIMMs for upgradeability too at bit lower speed.
Especially with how normal memory tiering is nowadays, especially in the datacenter (Intel’s bread and butter) now that you can stick a box of memory on a CXL network and put the memory from your last gen servers you just retired into said box for a third or fourth tier of memory before swapping. And the fun not tiered memory stuff the CXL enables. Really CXL just enables so much cool stuff that it’s going to be incredible once that starts hitting small single row datacenters