I believe they got a $0 license for the M0+ cores in the 2040. Don’t know about the new 2350. The addition of Risc-v cores might be a flex to defend against future issues with ARM.
Going from two PIO blocks to three seems timid. Why not hundreds, like one for each gpio pin? And maybe redesign the PIO to allow more than 32 instructions? They are tiny, anyway.
Anyone know if there is any software for the Risc-v cores so far? Compilers, Micropython, etc.
I believe they got a $0 license for the M0+ cores in the 2040. Don’t know about the new 2350. The addition of Risc-v cores might be a flex to defend against future issues with ARM.
Going from two PIO blocks to three seems timid. Why not hundreds, like one for each gpio pin? And maybe redesign the PIO to allow more than 32 instructions? They are tiny, anyway.
Anyone know if there is any software for the Risc-v cores so far? Compilers, Micropython, etc.