Yeah definitely!

Well, an open ISA is ok, but it doesn’t mean the HW is open, furthermore, open != libre/free. That said, you can use an open ISA, like risc-v, and have a totally closed uArch, incluiding backdoors, non user processors, and such. Even if the uArch, design, and whether HLS code or the resultin RTL code are open, then there’s sysntehesis into layout, as well as a bunch of libraries, you don’t really know of, and might be including spying mechanisms, backdoors and such. On HW, and particularly semiconductors, it’s pretty hard to really know if it’s clean, ethical, non spying, and so on. For sure, it’s pretty hard to get really open HW, not to mention libre/free HW.

If we don’t produce SoCs/ASICs, it’s pretty hard to tell. But even if you do your our own design really open and clean, you can’t design everything, you trust on vendors IP. Furthermore you end up trusting as well the vendors libraries for the final synthesis.

That’s the important part of increasing the use of non profit and open IP and libraries, that although they don’t guarantee nothing obscure will be included, that helps a lot. In the end, on semis, I doubt it’ll be easy to stop having to trust what the final SoC/ASIC will include. A final thought, most ASICs/Socs makers are fabless, meaning they send their layouts to a 3rd party which creates the masks and final pieces of silicon. And some, if not most, also subcontract the routing and placing prior to deliver the final layout, in whatever format its delivered, to the contracted fab. All that introduces places where additional stuff can be added, whether libraries wise, or intentional…

Just saying. But I’m glad more people gets more aware of the need on open HW at least, and having an open ISA is as good as any other starting point. Sadly, most advances are not done for non profitable organizations, but designing and building SoCs/ASICs really require capital.

I still would prefer risc-v based products though.